module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 

    parameter IDLE = 4'd0;
    parameter START = 4'd1;
    parameter D0 = 4'd2;
    parameter D1 = 4'd3;
    parameter D2 = 4'd4;
    parameter D3 = 4'd5;
    parameter D4 = 4'd6;
    parameter D5 = 4'd7;
    parameter D6 = 4'd8;
    parameter D7 = 4'd9;
    parameter STOP = 4'd10;
    parameter WAIT = 4'd11;
    
    reg	[3:0]	state;
    reg	[3:0]	next_state;
    
    always @(*) begin
        case(state)
            IDLE:begin
                if(!in) begin
                    next_state = START;
                end
                else begin
                    next_state = IDLE;
                end
            end
            START:begin
                next_state = D0;
            end
            D0:begin
                next_state = D1;
            end
            D1:begin
                next_state = D2;
            end
            D2:begin
                next_state = D3;
            end
            D3:begin
                next_state = D4;
            end
            D4:begin
                next_state = D5;
            end
            D5:begin
                next_state = D6;
            end
            D6:begin
                next_state = D7;
            end
            D7:begin
                if(in) begin
                    next_state = STOP;
                end
                else begin
                    next_state = WAIT;
                end
            end
            STOP:begin
                if(!in) begin
                    next_state = START;
                end
                else begin
                    next_state = IDLE;
                end
            end
            WAIT:begin
                if(in) begin
                    next_state = IDLE;
                end
                else begin
                    next_state = WAIT;
                end
            end
            default:next_state = IDLE;
        endcase
    end
    
    always @(posedge clk) begin
        if(reset) begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    assign done = (state == STOP);
    
endmodule
